在VHDL/ModelSim的

Question

我试图使用VHDL配置规范使用配置规格预先设定

这应该是可能的，如图IEEE1076-2008，节7.3.2.1，这给出了以下示例：

entity AND_GATE is 
    generic (I1toO, I2toO: DELAY_LENGTH := 4 ns); 
    port (I1, I2: in BIT; O: out BIT); 
end entity AND_GATE; 

entity XOR_GATE is 
    generic (I1toO, I2toO: DELAY_LENGTH := 4 ns); 
    port (I1, I2: in BIT; O: out BIT); 
end entity XOR_GATE; 

package MY_GATES is 
    component AND_GATE is 
     generic (I1toO, I2toO: DELAY_LENGTH := 4 ns); 
     port (I1, I2: in BIT; O: out BIT); 
    end component AND_GATE; 
    component XOR_GATE is 
     generic (I1toO, I2toO: DELAY_LENGTH := 4 ns); 
     port (I1, I2: in BIT; O: out BIT); 
    end component XOR_GATE; 
end package MY_GATES; 

entity Half_Adder is 
    port (X, Y: in BIT; Sum, Carry: out BIT); 
end entity Half_Adder; 

use WORK.MY_GATES.all; 

architecture Structure of Half_Adder is 
    for L1: XOR_GATE use 
     entity WORK.XOR_GATE(Behavior) -- The primary binding 
      generic map (3 ns, 3 ns) -- indication for instance L1. 
      port map (I1 => I1, I2 => I2, O => O); 
    for L2: AND_GATE use 
     entity WORK.AND_GATE(Behavior) -- The primary binding 
      generic map (3 ns, 4 ns) -- indication for instance L2. 
      port map (I1, open, O); 
begin 
    L1: XOR_GATE port map (X, Y, Sum); 
    L2: AND_GATE port map (X, Y, Carry); 
end architecture Structure; 

use WORK.GLOBAL_SIGNALS.all; 

configuration Different of Half_Adder is 
    for Structure 
     for L1: XOR_GATE 
      generic map (2.9 ns, 3.6 ns); -- The incremental binding 
     end for; -- indication of L1; rebinds its generics. 
     for L2: AND_GATE 
      generic map (2.8 ns, 3.25 ns) -- The incremental binding 
      port map (I2 => Tied_High); -- indication of L2; rebinds 
     end for; -- its generics and binds its open port. 
    end for; 
end configuration Different; 

即使我添加了包从这个例子里缺自己

package GLOBAL_SIGNALS is 
    constant Tied_High : bit := '1'; 
end package GLOBAL_SIGNALS; 

改进方案是在的ModelSim仍然失败。

Error: [...]/half_adder.vhd(36): (vcom-1035) Formal port "I2" has OPEN or no actual associated with it.

通过似乎已经表明的ModelSim不正确地支持这些配置语句行

port map (I1, open, O); 

引起的。

我想使用这个配置规范来缓解我的设计入门。

例子：

entity comp is 
    generic(step : time; defined: boolean); 
    port(clk, data : in bit); 
end entity; 

entity e is end entity e; 

architecture a of e is 
    component comp is 
     generic(step : time; defined: boolean); 
     port(clk, data : in bit); 
    end component; 

    signal clk1, clk2 : bit; 

    for a : comp use 
     entity work.comp 
      generic map(step => 1 ns) 
      port map(clk => clk1); 
    for b : comp use 
     entity work.comp 
      generic map(step => 100 ns) 
      port map(clk => clk2); 
    for all : comp use 
     entity work.comp 
      generic map(defined => true); 

    signal sig_a, sig_b : bit; 

begin 
    a: comp 
     port map(data => sig_a); 

    b_gen : for i in 0 to 2 generate 
     b: comp 
      port map(data => sig_b); 
    end generate; 
end architecture; 

该代码将引发大量的错误：

Error: [...]/e.vhd(19): (vcom-1031) Formal generic "defined" has OPEN or no actual associated with it.

Error: [...]/e.vhd(19): (vcom-1035) Formal port "data" has OPEN or no actual associated with it.

Error: [...]/e.vhd(23): (vcom-1031) Formal generic "defined" has OPEN or no actual associated with it.

Error: [...]/e.vhd(23): (vcom-1035) Formal port "data" has OPEN or no actual associated with it.

Error: [...]/e.vhd(26): (vcom-1031) Formal generic "step" has OPEN or no actual associated with it.

Error: [...]/e.vhd(24): ALL configuration specification for component "comp" attempts to re-bind instances already bound.

Error: [...]/e.vhd(24): ALL configuration specification for component "comp" attempts to re-bind instances already bound.

Error: [...]/e.vhd(32): (vcom-1031) Formal generic "step" has OPEN or no actual associated with it.

Error: [...]/e.vhd(32): (vcom-1031) Formal generic "defined" has OPEN or no actual associated with it.

Error: [...]/e.vhd(32): (vcom-1035) Formal port "clk" has OPEN or no actual associated with it.

Error: [...]/e.vhd(36): (vcom-1031) Formal generic "step" has OPEN or no actual associated with it.

Error: [...]/e.vhd(36): (vcom-1031) Formal generic "defined" has OPEN or no actual associated with it.

Error: [...]/e.vhd(36): (vcom-1035) Formal port "clk" has OPEN or no actual associated with it.

Warning: [...]/e.vhd(24): (vcom-1263) Configuration specification "all : comp" applies to no component instantiation statements.

Error: [...]/e.vhd(20): No statement with label "b" was found.

如此看来，这是不使用的配置规格的支持方式。太糟糕了，因为这会缓解我的设计入门。

我只是一个Modelsim错误，或配置规范永远不会帮助这些默认绑定？

Answer 1

这个问题已经改变，这个问题也有答案。

Modelsim中的精化仍然失败。

Error: [...]/half_adder.vhd(36): (vcom-1035) Formal port "I2" has OPEN or no actual associated with it.

通过似乎已经表明的ModelSim不正确地支持这些配置语句行

port map (I1, open, O); 

引起的。

VHDL标准不支持VHDL标准不支持的结论。

此错误似乎是由于未绑定I2时尝试详细说明Half_Adder而引起的。配置规范将I2与open关联，这是不允许的。

如果创建一个Minimal, Complete and Verifiable example：

-- IEEE Std 1076-1993 5.2.1 Binding Indication (example) 
-- -2008 7.3.2.1 

package global_signals is -- THIS PACKAGE MISSING IN THE EXAMPLE 
    signal Tied_High: bit := '1'; 
end package; 

entity AND_GATE is   -- ADDED entity and architecture 
    generic (I1toO, I2toO: DELAY_LENGTH := 4 ns); 
    port  (I1, I2: in BIT; O: out BIT); 
end entity AND_GATE; 

architecture Behavior of AND_GATE is -- ADDED 
    signal In1, In2: BIT; 
begin 
    In1 <= I1 after I1toO; 
    In2 <= I2 after I2toO; 

    O <= In1 and In2; 

    process 
    begin 
     report 
      LF & HT & "I1to0 = " & time'image(I1toO) & 
      LF & HT & "I2to0 = " & time'image(I2toO); 
     wait; 
    end process; 
end architecture Behavior; 

entity XOR_GATE is   -- ADDED entity and architecture 
    generic (I1toO, I2toO : DELAY_LENGTH := 4 ns); 
    port  (I1, I2: in BIT; O : out BIT); 
end entity XOR_GATE; 

architecture Behavior of XOR_GATE is -- ADDED 
    signal In1, In2: BIT; 
begin 
    In1 <= I1 after I1toO; 
    In2 <= I2 after I2toO; 

    O <= In1 xor In2; 

    process 
    begin 
     report 
      LF & HT & "I1to0 = " & time'image(I1toO) & 
      LF & HT & "I2to0 = " & time'image(I2toO); 
     wait; 
    end process; 
end architecture Behavior; 

package MY_GATES is 
    component AND_GATE is 
     generic (I1toO, I2toO: DELAY_LENGTH := 4 ns); 
     port  (I1, I2: in BIT; O: out BIT); 
    end component AND_GATE; 

    component XOR_GATE is 
     generic (I1toO, I2toO: DELAY_LENGTH := 4 ns); 
     port  (I1, I2: in BIT; O : out BIT); 
    end component XOR_GATE; 
end package MY_GATES; 

entity Half_Adder is 
    port (X, Y: in BIT; 
       Sum, Carry: out BIT); 
end entity Half_Adder; 

use WORK.MY_GATES.all; 
architecture Structure of Half_Adder is 
    signal O: bit;   -- Added 
    for L1: XOR_GATE use 
     entity WORK.XOR_GATE(Behavior)  -- The primary binding indication 
      generic map (3 ns, 3 ns)  -- for instance L1. 
      port map (I1 => I1, I2 => I2, O => O); 

    for L2: AND_GATE use 
     entity WORK.AND_GATE(Behavior)  -- The primary binding indication 
      -- generic map (3 ns, 4 ns)  -- for instance L2. 
      port map (I1, open, O); 

begin 
    L1: XOR_GATE port map (X, Y, Sum); 
    L2: AND_GATE port map (X, Y, Carry); 
end architecture Structure; 

use WORK.GLOBAL_SIGNALS.all; 

configuration Different of Half_Adder is 
    for Structure 
     for L1: XOR_GATE 
      generic map (2.9 ns, 3.6 ns); -- The incremental binding 
     end for;    -- indication of L1; rebinds its generics. 

     for L2: AND_GATE 
      generic map (2.8 ns, 3.25 ns) -- The incremental binding 
      port map (I2 => Tied_High); -- indication L2; rebinds its generics 
     end for;       -- and binds its open port. 
    end for; 
end configuration Different; 

在这种情况下

都在分析了一个设计文件，阐述和模拟：

ghdl -a Half_Adder.vhdl
ghdl -e different
ghdl -r different
Half_Adder.vhdl:44:9:@0ms:(report note): I1to0 = 2900000 fs I2to0 = 3600000 fs Half_Adder.vhdl:22:9:@0ms:(report note): I1to0 = 2800000 fs I2to0 = 3250000 fs

同时展示在代码的功能绑定表示正常增量。

请注意，这需要从包含最近Github提交的源代码构建的ghdl实现。

提交：9e0cf4af3cf2141002b37db9803c15afec8ea2f4 [9e0cf4a]
父母：b801510561
著者：特里斯坦Gingold
日期：2017年10月30日在上午7时19分41秒GMT + 13

分析，制定和运行上述Half_Adder需要在2017年10月30日之后从Github存储库构建的ghdl，能够随着最近恢复的语义分析应用方式而意外丢失。发布时的能力将在ghdl-0.35。

没有人注意到这段时间缺乏几年。这个功能可能不如增量绑定的作者所期望的那么热烈。您也可以注意到标准中的示例不完整，并且在以后的修订中会显示其他错字。 MCVe现已被纳入ghdl的测试套件。

您生成的第二个示例代码（e.vhdl）不提供配置声明。

Annex I (Informative) Glossary

incremental binding: A binding indication in a configuration declaration that either reassociates a previously associated local generic constant or that associates a previously unassociated local port is said to incrementally rebind the component instance or instances to which the binding indication applies. (7.3.2.1)

这个'限制'是如何产生的，这是语义要求的问题。

对Jean-MichelBergé，Alain Fonkoua，Serge Maginot和Jacques Rouillard的书“VHDL'92”中作者的增量约束理解可以从中得到。参见VHDL'92,6。增量绑定，第47至56页。

（增量绑定也可以在IEEE Std P1076-1992c中发现，随后并入IEEE Std 1076-1993修订版）。

有你的第二个例子不同的语义缺点：

e.vhdl：

entity comp is 
    generic(step : time; defined: boolean); 
    port(clk, data : in bit); 
end entity; 

entity e is end entity e; 

architecture a of e is 
    component comp is 
     generic(step : time; defined: boolean); 
     port(clk, data : in bit); 
    end component; 

    signal clk1, clk2 : bit; 

    for a : comp use 
     entity work.comp 
      generic map(step => 1 ns) 
      port map(clk => clk1); 
    for b : comp use 
     entity work.comp 
      generic map(step => 100 ns) 
      port map(clk => clk2); 
    for all : comp use 
     entity work.comp 
      generic map(defined => true); 

    signal sig_a, sig_b : bit; 

begin 
    a: comp 
     port map(data => sig_a); 

    b_gen : for i in 0 to 2 generate 
     b: comp 
      port map(data => sig_b); 
    end generate; 
end architecture; 

除了缺少的配置声明中，例如，通过Modelsim的错误和警告表明这些不足以及ghdl：

ghdl -a e.vhdl 
e.vhdl:31:5:error: no actual for constant interface "step" 
e.vhdl:35:9:error: no actual for constant interface "step" 
e.vhdl:20:9:error: no component instantation with label "b" 
e.vhdl:24:5:error: component instance "a" is already bound by a configuration specification 
e.vhdl:16:5:error: (previous is configuration specification) 
ghdl:error: compilation error 

综合工具通常支持配置规范，但不支持配置声明。当应用于硅片设计时，增量式绑定并没有真正的实际用途。