S32K系列S32K144学习笔记——UART2
S32K系列S32K144学习笔记——UART2
本例程，以MCU为S32K144，开发平台S32DSworkspace
功能描述：配置UART2，输出打印“just do it!” ，把RX接收到的数据，通过TX发出去
如有错误，麻烦帮忙指出，谢谢！
#include "S32K144.h" /* include peripheral declarations S32K144 */
#include "s32_core_cm4.h"
void WDOG_disable (void)
{
WDOG->CNT=0xD928C520; //解锁看门狗
WDOG->TOVAL=0x0000FFFF; //把时间配置为最大
WDOG->CS = 0x00002100; //关闭看门狗
}
void SOSC_init_8MHz(void)
{
SCG->SOSCDIV=0x00000101; // SOSCDIV1 & SOSCDIV2 =1: divide by 1
SCG->SOSCCFG=0x00000024; /* Range=2: Medium freq (SOSC betw 1MHz-8MHz)*/
/* HGO=0: Config xtal osc for low power */
/* EREFS=1: Input is external XTAL */
while(SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK); /* Ensure SOSCCSR unlocked */
SCG->SOSCCSR=0x00000001; /* LK=0: SOSCCSR can be written */
/* SOSCCMRE=0: OSC CLK monitor IRQ if enabled */
/* SOSCCM=0: OSC CLK monitor disabled */
/* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled */
/* SOSCLPEN=0: Sys OSC disabled in VLP modes */
/* SOSCSTEN=0: Sys OSC disabled in Stop modes */
/* SOSCEN=1: Enable oscillator */
while(!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)); /* Wait for sys OSC clk valid */
}
void SPLL_init_160MHz(void)
{
while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */
SCG->SPLLCSR = 0x00000000; /* SPLLEN=0: SPLL is disabled (default) */
SCG->SPLLDIV = 0x00000302; /* SPLLDIV1 divide by 2; SPLLDIV2 divide by 4 */
SCG->SPLLCFG = 0x00180000; /* PREDIV=0: Divide SOSC_CLK by 0+1=1 */
/* MULT=24: Multiply sys pll by 4+24=40 */
/* SPLL_CLK = 8MHz / 1 * 40 / 2 = 160 MHz */
while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */
SCG->SPLLCSR = 0x00000001; /* LK=0: SPLLCSR can be written */
/* SPLLCMRE=0: SPLL CLK monitor IRQ if enabled */
/* SPLLCM=0: SPLL CLK monitor disabled */
/* SPLLSTEN=0: SPLL disabled in Stop modes */
/* SPLLEN=1: Enable SPLL */
while(!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)); /* Wait for SPLL valid */
}
void NormalRUNmode_40MHz (void)
{
/* Change to normal RUN mode with 8MHz SOSC, 80 MHz PLL*/
SCG->RCCR=SCG_RCCR_SCS(6) /* PLL as clock source*/
|SCG_RCCR_DIVCORE(0b11) /* DIVCORE=3, div. by 4: Core clock = 160/4 MHz = 40 MHz*/
|SCG_RCCR_DIVBUS(0b11) /* DIVBUS=3, div. by 4: bus clock = 160/4 MHz = 40 MHz*/
|SCG_RCCR_DIVSLOW(0b111); /* DIVSLOW=7, div. by 8: SCG slow, flash clock= 160/8 MHz = 20MHZ*/
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6) {}
/* Wait for sys clk src = SPLL */
}
void UART2_NVIC_init_IRQs(void)
{
S32_NVIC->ICPR[1] = 1 << (35 % 32); /* IRQ48-UART2: clr any pending IRQ*/
S32_NVIC->ISER[(uint32_t)(LPUART2_RxTx_IRQn) >> 5U] = (uint32_t)(1UL << ((uint32_t)(LPUART2_RxTx_IRQn) & (uint32_t)0x1FU));
S32_NVIC->IP[35] = 0x7; /* IRQ48-UART2: priority 7 of 0-15*/
}
void UART2_PORT_init (void)
{
PCC->PCCn[PCC_PORTA_INDEX ] |= PCC_PCCn_CGC_MASK; /* Enable clock for PORTA */
PORTA->PCR[8] |= PORT_PCR_MUX(2); /* Port A8: MUX = ALT2,UART2 RX */
PORTA->PCR[9] |= PORT_PCR_MUX(2); /* Port A9: MUX = ALT2,UART2 TX */
}
void UART2_init(void) /* Init. summary: 9600 baud, 1 stop bit, 8 bit format, no parity */
{
PCC->PCCn[PCC_LPUART2_INDEX] &= ~PCC_PCCn_CGC_MASK; /* Ensure clk disabled for config */
PCC->PCCn[PCC_LPUART2_INDEX] |= PCC_PCCn_PCS(0b001) /* Clock Src= 1 (SOSCDIV2_CLK) */
| PCC_PCCn_CGC_MASK; /* Enable clock for LPUART2 regs */
LPUART2->BAUD = 0x0F000034; /* Initialize for 9600 baud, 1 stop: */
/* SBR=52 (0x34): baud divisor = 8M/9600/16 = ~52 */
/* OSR=15: Over sampling ratio = 15+1=16 */
/* SBNS=0: One stop bit */
/* BOTHEDGE=0: receiver samples only on rising edge */
/* M10=0: Rx and Tx use 7 to 9 bit data characters */
/* RESYNCDIS=0: Resync during rec'd data word supported */
/* LBKDIE, RXEDGIE=0: interrupts disable */
/* TDMAE, RDMAE, TDMAE=0: DMA requests disabled */
/* MAEN1, MAEN2, MATCFG=0: Match disabled */
LPUART2->CTRL=0x000C0000 | (1<<28); /* Enable transmitter & receiver, no parity, 8 bit char: */
/* RE=1: Receiver enabled */
/* TE=1: Transmitter enabled */
/* PE,PT=0: No hw parity generation or checking */
/* M7,M,R8T9,R9T8=0: 8-bit data characters*/
/* DOZEEN=0: LPUART enabled in Doze mode */
/* ORIE,NEIE,FEIE,PEIE,TIE,TCIE,RIE,ILIE,MA1IE,MA2IE=0: no IRQ*/
/* TxDIR=0: TxD pin is input if in single-wire mode */
/* TXINV=0: TRansmit data not inverted */
/* RWU,WAKE=0: normal operation; rcvr not in statndby */
/* IDLCFG=0: one idle character */
/* ILT=0: Idle char bit count starts after start bit */
/* SBK=0: Normal transmitter operation - no break char */
/* LOOPS,RSRC=0: no loop back */
LPUART2->CTRL|= 0x00200000;//使能接收中断
}
void UART2_transmit_string(char data_string[],int len)
{
uint32_t i=0;
for(i=0;i<len;i++)
{
UART2_transmit_char(data_string[i]);
}
UART2_transmit_char('\n'); /* New line */
UART2_transmit_char('\r'); /* Return */
}
void _printf(char data_string[])
{
UART2_transmit_string(data_string,strlen(data_string));
UART2_transmit_char('\n'); /* New line */
UART2_transmit_char('\r'); /* Return */
}
int main(void)
{
WDOG_disable(); //关闭看门狗
SOSC_init_8MHz(); //配置系统振荡器为外部8MHZ
SPLL_init_160MHz(); //使用SOSC 8MHZ配置SPLL 为160 MHz
NormalRUNmode_40MHz(); //配置系列时钟40MHz, 40MHz总线时钟
UART2_init(): //配置UART2 波特率9600 1个停止数 无校验位
UART2_NVIC_init_IRQs(); //配置中断优先级
UART2_PORT_init (): //配置GPIO复用为TX、RX
_printf("just do it!");
while(1)
{
}
return 0;
}
void LPUART2_RxTx_IRQHandler(void)
{
char rev;
if (LPUART2->STAT & 0x00200000)
{
rev = LPUART2->DATA;
if((LPUART2->STAT & LPUART_STAT_TDRE_MASK)>>LPUART_STAT_TDRE_SHIFT!=0) //判断发射是否空闲
{
LPUART2->DATA = rev;
}
}
}