两抽头自适应LMS FIR滤波器的VHDL程序，具有两个系数f0,f1，步长u=0.25的二阶滤波器

程序正文：
LIBRARY LPM;
USE LPM.LPM_COMPONENTS.ALL;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;

ENTITY LMS_FIR IS
GENERIC (W1:INTEGER:=8;
W2:INTEGER:=16;
L:INTEGER:=2);
PORT (CLK:IN STD_LOGIC;
X_IN:IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
D_IN:IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
E_OUT,Y_OUT:OUT STD_LOGIC_VECTOR(W2-1 DOWNTO 0);
F0_OUT,F1_OUT:OUT STD_LOGIC_VECTOR(W1-1 DOWNTO 0));
END LMS_FIR;

ARCHITECTURE FLEX OF LMS_FIR IS

SUBTYPE N1BIT IS STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
SUBTYPE N2BIT IS STD_LOGIC_VECTOR(W2-1 DOWNTO 0);
TYPE ARRAY_N1BIT IS ARRAY (0 TO L-1) OF N1BIT;
TYPE ARRAY_N2BIT IS ARRAY (0 TO L-1) OF N2BIT;

SIGNAL D :N1BIT;
SIGNAL EMU:N1BIT;
SIGNAL Y,SXTY:N2BIT;

SIGNAL E,SXTD:N2BIT;
SIGNAL X,F:ARRAY_N1BIT;
SIGNAL P,XEMU:ARRAY_N2BIT;

BEGIN

DSXT:PROCESS(D)
BEGIN
SXTD(7 DOWNTO 0) <= D;
FOR K IN 15 DOWNTO 8 LOOP
SXTD(K) <= D(D’HIGH);
END LOOP;
END PROCESS;
STORE:PROCESS
BEGIN
WAIT UNTIL CLK=‘1’;
D <= D_IN;
X(0) <= X_IN;
X(1) <= X(0);
F(0) <= F(0)+XEMU(0)(15 DOWNTO 8);
F(1) <= F(1)+XEMU(1)(15 DOWNTO 8);
END PROCESS STORE;

MULGEN1:FOR I IN 0 TO L-1 GENERATE
FIR:LPM_MULT
GENERIC MAP ( LPM_WIDTHA => W1,LPM_WIDTHB => W1,
LPM_REPRESENTATION => “SIGNED”,
LPM_WIDTHP => W2,
LPM_WIDTHS => W2)
PORT MAP ( DATAA =>X(I),DATAB=>F(I),RESULT => P(I));
END GENERATE;

Y <= P(0)+P(1);
YSXT:PROCESS (Y)
BEGIN
SXTY(8 DOWNTO 0) <= Y(15 DOWNTO 7);
FOR K IN 15 DOWNTO 9 LOOP
SXTY(K) <= Y(Y’HIGH);
END LOOP;
END PROCESS;

E<=SXTD - SXTY;
EMU <= E(8 DOWNTO 1);

MULGEN2:FOR I IN 0 TO L-1 GENERATE
FUPDATE: LPM_MULT
GENERIC MAP (
LPM_WIDTHA => W1,
LPM_WIDTHB => W1,
LPM_REPRESENTATION => “SIGNED”,
LPM_WIDTHP => W2,
LPM_WIDTHS => W2)
PORT MAP (DATAA=>X(I),
DATAB=>EMU,
RESULT => XEMU(I));
END GENERATE;

Y_OUT <= Y;
E_OUT <= E;
F0_OUT <= F(0);
F1_OUT <= F(1);

END FLEX;
仿真结果：