Verilog HDL**两位数码管计数器，关于reg位数的问题

顶层原理图

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
count.v

module count(
   input sys_clk,
   input sys_rst_n,
   
   output reg [7:0] data);             //累加数
   
parameter MAX_TIME = 25'd25000_000;     //25M频率1s
parameter MAX_NUM = 99;                 //最大计数到99
reg [25:0] cnt;                         //计数    
reg [7:0] data_tmp;
reg [7:0] point_tmp;
reg flag;                               //计数周期标志，1s产生一个脉冲

//分频得出1s
always @(posedge sys_clk or negedge sys_rst_n) begin
   if(!sys_rst_n) begin
       cnt <= 25'd0;
       flag <= 1'b0;
   end
   else if(cnt < MAX_TIME) begin
       cnt <= cnt+1'b1;
       flag <= 1'b0;
   end
   else begin
       flag <= 1'b1;
       cnt <= 25'd0;
   end
end

//data 自加
always @(posedge sys_clk or negedge sys_rst_n) begin
   if(!sys_rst_n)  begin
       data_tmp <= 12'd0;
       point_tmp<= 2'd0;
   end
   else if(flag) begin
       if(data_tmp < MAX_NUM)
           data_tmp <= data_tmp + 1;
       else
           data_tmp <= 12'd0;
   end
   else
       data_tmp <= data_tmp;
       
   data <= data_tmp;
end
   
   
endmodule

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
3. seg_led_set.v

module seg_led_set(
    input sys_clk,
    input sys_rst_n,
    
    input [7:0] data,
    
    output reg [1:0] sel,
    output reg [7:0] led);    
//
parameter TIME_1ms = 15_000;        //数码管1ms循环闪烁

reg [3:0]   num_dis;                //当前显示的数
reg [1:0]   sel_dis;                //当前显示的位
reg         clk_div;                //1ms 分频
reg [14:0]  clk_cnt;                //1ms 分频 计数器  15000是14位，但是clk_cnt不能定义为reg[13:0],这是为何？

wire [3:0] data0;                   //个位
wire [3:0] data1;                   //十位    

assign data0 = data%10;
assign data1 = data/10%10;

//分频得出1ms翻转一次的clk_div
always @(posedge sys_clk or negedge sys_rst_n) begin
    if(!sys_rst_n) begin
        clk_cnt <= 14'd0;
        clk_div <= 1'b0;
    end
    else if(clk_cnt < TIME_1ms)
        clk_cnt <= clk_cnt + 1'b1;
    else begin
        clk_cnt <= 14'd0;
        clk_div <= ~clk_div;
    end
end 

//根据clk_div的状态选择点亮十位或者各位的数码管
always @(posedge sys_clk or negedge sys_rst_n) begin
    if(!sys_rst_n) begin
        num_dis <= 4'd0;
        sel <= 2'd0;
    end
    else if(clk_div) begin
        sel <= 2'b10;
        num_dis <= data1;
    end
    else begin
        sel <= 2'b01;
        num_dis <= data0;
    end
end

//译码输出
always @(posedge sys_clk or negedge sys_rst_n) begin
    if(!sys_rst_n)
        led <= 8'hff;
    else begin
        case (num_dis)
            4'h0: led <= 8'b0011_1111;
            4'h1: led <= 8'b0000_0110;
            4'h2: led <= 8'b0101_1011;
            4'h3: led <= 8'b0100_1111;
            4'h4: led <= 8'b0110_0110;
            4'h5: led <= 8'b0110_1101;
            4'h6: led <= 8'b0111_1101;
            4'h7: led <= 8'b0000_0111;
            4'h8: led <= 8'b0111_1111;
            4'h9: led <= 8'b0110_0111;
            4'ha: led <= 8'b0111_0111;
            4'hb: led <= 8'b0111_1100;
            4'hc: led <= 8'b0011_1001;
            4'hd: led <= 8'b0101_1110;
            4'he: led <= 8'b0111_1001;
            4'hf: led <= 8'b0111_0001;
        default : led <= 8'b0011_1111;
        endcase
    end
end  
endmodule

实现两位数码管显示从00累加到99的秒计时器，遗留问题是cnt计1ms时在15M晶振频率下要记到15000，15000是14位，在seg_led_set.v中，cnt如果定义为reg [13:0]，则无法计到15000，目前尚未查出原因。

Verilog HDL**两位数码管计数器，关于reg位数的问题

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