引言

本文在上一讲逐渐熟悉了VCS的开关选项后，下面继续介绍VCS的使用，我始终关注于熟悉工具的使用，在本系列中，对Verilog的语法不作深入研究，这样可以加快前进的步伐。也为了加快从FPGA中转变到IC领域来。在本文中将介绍VCS 调试基础。

1、基础理论讲义

—Afer completing this unit ,you should be able to:

1. Describe three methods of debugging Verilog code using VCS
2. Invoke UCLI debugger
3. Debug Verilog designs using UCLI

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–VCS Debugging Suport
4. Trance and locate causes of errors
5. Three general debugging methods:

6. Verilog SystemVerilog System Task calls
   VCS UCLI
   VCS DVE(GUI)

7. Four factors to consider:
   simulation speed
   signal visibility
   sgnal tractability
   usability

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Verilog System Task For Debugging 利用verilog的系统函数

1. Debug visibility:

• $ display prints formatted message to console
• $ strobe Like$dispaly except printing is delayed until all events in the current time step have executed
• $ monitor Monitor signals listed and prints formatted message whenever one of the listed signals changes
• $ time returns current simulation time as a 64bits integer

2. Stopping simulations:
   $stop halts simulation lie a breakpoint
   $finish halts simulation and terminated the simulation session

3. Simulation stimulus and reference:

• $readmemh Reads ASCII data from a disk file,each digit is hexadecimal -$readmemhReadsASCIIdatafromadiskfile,eachdigitishexadecimal− readmemb
  Reads ASCII dataform a disk file ,Each digit is binary

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Debugging via UCLI(no-recom)不推荐使用UCLI方式来查看波形

• Simulation speed
  Speed depends on the scale of visibility you specify
• Signal Vsisibiility
• Signal Traceability
  -Usability

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Compile and Invoke UCLI Debugger

-Compile and invoke UCLI in one step(一步走，编译并且调用UCLI)

$ vcs source.v -debug|debug_all -R -ucli
-ucli invokes UCLI and stop simulation time at time 0

-Compile and invoke UCLI in two step(分两步走，先编译，后执行可执行文件)
vcs source.v -debug|debug_all|debug_pp(debug_pp只打开部分调试开关，加快编译速度)
invoke UCLI and stop simulation time at time 0
$simv -ucli

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UCLI Debugger Command Line Option

-debug
enables command line debugging option. This flag does not enable line stepping.

-debug_all
enables command line debugging option including line stepping

-ucli
forces runtime to go into UCI mode by default

-gui
compile time option invokes the DVE gui when issured at run time

-l log_filename
captures simulation output ,such as user input UCLI commands and responses to UCLI commands.

-i input_filename
reads interactive UCLI commands from a file the switches readding from standard command line input

-k key_filename
writes interactive commands entered to input_filename,which can be used by a latter simv as -i input_filename
由于UCLI的陈旧，这里不再强调。

退出UCLI
quit 即可

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Problems in simulation?
if you suspect simlation is having problems

Determine whether or not time is advancing:
halt simulation by hiting ctrl+c 通过ctrl+c来退出仿真

check simulation time

continue simulation by typing in run at UCLI prompt
halt simulation again after a shor period of time

if simulation time has not changed,simulation may be caught in infinite loop or waiting for a phantom triger

-Determine potential location of problem:
Re-compile with -debug_all compile-time option
halt simulation
use UCLI command show to dispaly variables
trace code execution with UCLI command next

官方的文档位置：

2 使用UCLI来debug

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DVE（Discovery Visual Environment）
An intuitive and easy to use GUI
Quiickly fine bugs
RTL or Gates
Assertions
Testbench
Supports
Interactive
Post-simulaton analisis
Multiple languages
verilog
VHDL
SV
C++、C
NTB

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波性文件vpd
verdi里面的波性文件为fsdb

比较两个信号