Notes: Hardware-based Acceleration Design 20200226
16. Static Timing Analysis (STA)
16.1. Overview
Time constraint verificaiton without simulation
- Faster than gate-level simulation
- No checking on cirtuit correctness
- No vector generated.
Recall the position of STA:
16.2. STA from outside
Main tool: Synopsis Prime Time
16.3. Basic concept
- setup time, stable data time before the clock transition
- hold time, stabbel data time after the clock transition
- time slack, arrivingtime - setup time, holding time - leaving time
16.4. Main steps
16.5. Paths
Focus on UFF1, the launch path and the capture path offer the time periods to calculate.
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